FIG. 28 is a block diagram showing a conventional solid-state image sensing apparatus, FIG. 29 is a circuit diagram showing a periphery of 1 pixel part which configures the solid-state image sensing apparatus of FIG. 28, and FIG. 30 is a timing chart showing operations of the circuit which was shown in FIG. 29.
A solid-state image sensing apparatus 102 which was shown in FIG. 28 is concretely a CMOS light sensor, and includes a pixel region 104 which was formed on a semiconductor substrate, V selection means 106, H selection means 108, a timing generator 110 (TG), a signal processing part 112, a constant current part 114A and so on. In the pixel region 104, a lot of pixels are disposed in a matrix shape, and it is configured such that electric signals which were generated due to each pixel's detecting light, on the basis of a timing pulse from the timing generator 110, are sequentially selected by the V selection means 106 and the H selection means 108, and outputted from a horizontal signal line 116 through an output part 118.
A pixel 120, as shown in FIG. 29, is configured by including a photo diode 122, a floating diffusion part 124 (FD part 124) which generates a voltage of a size which corresponded to an amount of electrical charges, a transfer gate 126 which connects the photo diode 122 to the FD part 124 when a transfer pulse was supplied, a reset gate 128 which connects the FD part 124 to an electric source Vdd when a reset pulse was supplied, and a buffer circuit 130 which outputs a voltage of the FD part 124.
The photo diode 122 is configured such that an anode is connected to ground, and a cathode is connected to a source of a MOSFET (MOS Field Effect Transistor) of N type which configures the transfer gate 126. A drain of the same MOSFET is connected to the FD part 124, and also, to a gate, a transfer pulse 132 is supplied from the timing generator 110. The reset gate 128 is also configured by a MOSSFET of N type, and its source is connected to the FD part 124, and a drain is connected to the electric source Vdd, respectively, and to a gate, a reset pulse 134 is supplied from the timing generator 110.
A gate of a MOSFET of N type which configures the buffer circuit 130 is connected to the FD part 124, and a drain is connected to the electric source Vdd. Between the buffer circuit 130 and a vertical signal line 136, an address gate 138 which comprises a MOSFET of N type exists, and to its gate, an address pulse 140 is supplied from the V selection means 106. And, a source of the buffer circuit 130 is connected to a drain of the address gate 138, and a source of the address gate 138 is connected to the vertical signal line 136.
The vertical signal line 136 is disposes with respect to each column of the pixel 120 which was arranged in a matrix shape, and a source of the address gate 138 of the pixel 120 which belongs to the same column is all connected to the corresponding vertical signal line 136. On end of the vertical signal line 136 is connected to a constant current source 114 in the constant current part 114A which was disposed outside the pixel region 104, and a constant current is made to flow through the vertical signal line 136. The other end of the vertical signal line 136 is connected to a signal processing part 112 which was disposed outside the pixel region 104.
In the signal processing part 112, with respect to each vertical signal line 136, first and second sample hold circuits 142, 144, CDS (Correlated Double Sampling) circuit 146 (first arithmetic circuit) and so on are disposed. The first and second sample hold circuits 142, 144, first and second sampling pulses 148, 150 being supplied thereto from the timing generator 110, holds a signal voltage which the buffer circuit 130 outputted to the vertical signal line 136. The CDS circuit 146 calculates a difference of voltages which these first and second sample hold circuits 142, 144 held.
Output signals of the CDS circuit 146 with respect to each vertical signal line 136 are sequentially selected by the H selection means 108 which operates on the basis of a timing signal from the timing generator 110, and outputted to the horizontal signal line 116, and outputted through the output part 118. The output part 118 is configured in detail by an amplification circuit, an AGC circuit, an A/D converter and so on.
Next, an operation of the solid-state image sensing apparatus 102 which was configured in this manner will be explained with also reference to FIG. 30, and centrally on an operation in the pixel 120.
The V selection means 106 operates on the basis of the timing pulse from the timing generator 110, and selects a row of the pixel region 104, and outputs the address pulse 140 (high level) at timing T1, to the pixel 120 which belongs to the selected row. This address pulse 140 is supplied to the address gate 138 in each pixel 120, and as a result, the address gate 138 is turned ON, and the buffer circuit 130 is connected to the vertical signal line 136.
Next, the timing generator 110 outputs the reset pulse 134 at timing T2, and by this, the reset gate 128 is turned ON, and the FD part 124 is connected to the electric source Vdd, and electric charges (electrons) which are stored in the FD part 124 are excluded. And, a voltage of the FD part 124 in this reset state is outputted to the vertical signal line 136 by the buffer circuit 130.
In passing, since the buffer circuit 130 forms a source follower circuit together with the constant current source 114, when the address gate 138 is ON, a gate voltage, i.e., a voltage which followed the voltage of the FD part 124, is outputted from the buffer circuit 130 to the vertical signal line 136 with low impedance.
Subsequently, at timing T3, the timing generator 110 outputs the first sampling pulse 148 to each first sample hold circuit 142 which was disposed with respect to each vertical signal line 136, and has a voltage, which was outputted to the vertical signal line 136 by the buffer circuit 130, held.
After that, at timing T4, the timing generator 110 outputs the transfer pulse 132, and has the transfer gate 126 turned ON, and has electric charges (electrons), which were stored due to such a fact that the photo diode 122 received light up to the timing T4, transferred to the FD part 124. The FD part 124 generates a voltage which corresponded to an amount of electric charges transferred, and the buffer circuit 130 outputs its voltage to the vertical signal line 136 with low impedance.
And, the timing generator 110, at timing T5, outputs the second sampling pulse 150 to each second sample hold circuit 144 which was disposed with respect to each vertical signal line 136, and at this time, has a voltage, which the buffer circuit 130 outputs to the vertical signal line 136, held. By this, the CDS circuit 146, which was disposed with respect to each vertical signal line 136, calculates a difference of a voltage at the time of reset which the first sample hold circuit 142 is holding and a voltage that the second sample hold circuit 144 is holding, and removes an offset portion, and outputs a voltage of a size which corresponds to an amount of received light of the photo diode 122.
In passing, since the above-described offset portion has different size with respect to each pixel 120, by removing the offset portion by the CDS circuit 146 in this manner, it is possible to remove noises due to variation of offset.
Output signals of the CDS circuit 146 with respect to each vertical signal line 136, on the basis of the timing pulse from the timing generator 110, are sequentially selected by the H selection means 108 and outputted to the horizontal signal line 116, and outputted as an image signal through the output part 118.
The V selection means 106, at timing T6, returns the address pulse 140 to a low level, and as a result, the address gate 138 is turned OFF and the buffer circuit 130 is cut off from the vertical signal line 136, and an operation regarding the pixel 120 which is of 1 row portion is completed.
Thereafter, the V selection means 106 operates on the basis of the timing pulse from the timing generator 110, and sequentially selects each row of the pixel 120. And, the above-described operation is carried out with respect to each row, and when the V selection means 106 selected all rows, image signals of 1 sheet portion of an image which was generated by all pixels 120 is to have been outputted.
However, in the such like solid-state image sensing apparatus 102, it was only possible to detect such a range that electric charges which the photo diode 122 generated overflow, i.e., an amount of light with a range up to a saturation level of the photo diode 122. Therefore, for example, in case that a diaphragm and shutter speed were fit in a dark portion of an object of shooting, the photo diode 122 is saturated at a bright portion of the object of shooting, and therefore, the entirety is shot as for example, stark white and it was impossible to obtain an image.
In order to realize a solution of this problem, in JP-A-11-313257 gazette, disclosed is a solid-state image sensing device in which a dynamic range was expanded by configuring such that a signal which corresponded to logarithm of an amount of received light is outputted. However, in this solid-state image sensing device, for the reason that a capacitor is used, there are such defects that its charging and discharging takes time, and a residual image occurs. And, since it is not possible to use an embedded photo diode (between an insulation film on a photo diode surface and a photo diode, for example, a P+ layer is formed) which has structurally an advantage of less noises, there is such a problem that image quality is inferior. And, since there are many constituent elements of a pixel circuit, miniaturization is difficult.
Also, also known is a such a technique that shooting is carried out with such short time and sufficiently long time that the photo diode 122 is not saturated by changing the shutter speed, therefore electric charge storage time in the photo diode 122, and by combining each shot image, a dynamic range is expanded, but in this method, for the reason that a line memory and a frame memory are required, an apparatus grows in size, and also, cost becomes high. And, since 2 signals with different light exposure periods are combined, application to a moving object of shooting is difficult. Further, also known is such a technology that, by changing electric charge storage time between adjacent rows of the pixel region 104, a memory becomes unnecessary, but in this technology, since calculation processing between adjacent rows is required, an apparatus grows in size, and also, a structure becomes complex. Further, since 1 signal is generated by 2 pixels, resolution is deteriorated.
This invention is one which was made to solve the suchlike problems, and its object is to provide a solid-state image sensing apparatus and its driving method which has a wide dynamic range, and is of high performance, and further, is of small size, and of low cost.